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Normalize all passepartout-economics to inline wiki links

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Replaced every bottom-of-section 'See also:' block with inline
Org-mode file: links at the first natural mention in body text.
All 29 files across the economics directory now use wiki-style
inline cross-references rather than standalone reference blocks.
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Hermes
2026-05-23 05:58:18 +00:00
parent 5a2fce162a
commit 3063f8fdf7
28 changed files with 56 additions and 123 deletions
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ideas/passepartout-economics/verification-appliance.org
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#+title: Verification Appliance (Hardware)
#+filetags: :passepartout:revenue:hardware:fpga:tenstorrent:
An FPGA or Tenstorrent card pre-loaded with a mature Passepartout image, domain-specific gate rules, and a hardware root of trust. No cloud dependency.
An FPGA or Tenstorrent card pre-loaded with a mature Passepartout image, [[file:domain-gate-packages.org][domain-specific gate rules]], and a hardware root of trust. No cloud dependency.
**Target:** regulated industries needing provable compliance that cannot accept cloud-based AI.
**Target:** regulated industries needing [[file:evaluation-harness.org][provable compliance]] that cannot accept cloud-based AI.
**Price:** $5K-$50K/unit. **Volume:** hundreds to low thousands in year one.
The Lisp Machine on Tenstorrent P150 (~72 RISC-V Tensix cores on a PCIe card) is the realistic first target: the microcode is RISC-V assembly (software), not FPGA bitstream (hardware). The system can propose, load, test, and roll back a new dispatch routine in seconds. An FPGA path would add synthesis time (minutes to hours per iteration).
The [[file:self-driving-lisp-machine.org][Lisp Machine]] on Tenstorrent P150 (~72 RISC-V Tensix cores on a PCIe card) is the realistic first target: the microcode is RISC-V assembly (software), not FPGA bitstream (hardware). The system can propose, load, test, and roll back a new dispatch routine in seconds. An FPGA path would add synthesis time (minutes to hours per iteration). This hardware-first approach embodies [[file:lisp-economics.org][Lisp economics]] — verification hardware has near-zero marginal cost. The [[file:upgrade-lifecycle.org][Upgrade lifecycle]] for the appliance is managed via signed firmware updates with Merkle snapshots.
Revenue estimate: 50 sales in year one = $250K-$2.5M.
See also: [[file:domain-gate-packages.org][Domain gate packages]], [[file:evaluation-harness.org][Evaluation harness]], [[file:self-driving-lisp-machine.org][Self-driving Lisp Machine]], [[file:lisp-economics.org][Lisp economics]], [[file:upgrade-lifecycle.org][Upgrade lifecycle]]