Stages: rename titles, fix execution order, remove all numbered references

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Hermes
2026-06-04 20:04:34 +00:00
parent 5ac701e8ec
commit 8b1b481828
22 changed files with 96 additions and 96 deletions

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@@ -70,9 +70,9 @@ Alternative: start with 4×64GB to get half bandwidth without crippling storage
* Strategic framing
This node is a bootstrap between Stage 0 (current, conventional) and Stages 3-4 (Lisp machine, bare-metal, in-process LLM on dedicated silicon). DDR4's bandwidth ceiling won't matter because:
This node is a bootstrap between Development (current, conventional) and Lisp Machine and AI Inference. DDR4's bandwidth ceiling won't matter because:
- Proxmox + ZFS + the Gate (Stage 2) don't stress 8-channel DDR4-3200
- Proxmox + ZFS + the Gate (Neurosymbolic Agent stage) don't stress 8-channel DDR4-3200
- GPU inference uses its own VRAM, not system memory
- By the time the Lisp machine arrives (different hardware entirely), this node graduates to NAS / Proxmox host duty