Add two new nodes: Lisp Machine security (PMP/ECALL architecture) and Common Logic relevance analysis

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Hermes
2026-05-21 19:59:59 +00:00
parent 303e8c6306
commit db253a70d5
4 changed files with 166 additions and 1 deletions

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@@ -14,4 +14,4 @@ Every subdomain involved is software — the most codifiable domain. RISC-V ISA,
The Tenstorrent approach is dramatically simpler than FPGA because the microcode is RISC-V assembly (software), not FPGA bitstream (hardware with minutes-per-iteration synthesis).
See also: [[file:verification-appliance.org][Verification appliance]], [[file:time-estimates.org][Time estimates]], [[file:sufficiency-flip.org][Sufficiency flip]], [[file:upgrade-lifecycle.org][Upgrade lifecycle]], [[file:lisp-economics.org][Lisp economics]]
See also: [[file:lisp-machine-security.org][Lisp Machine security]], [[file:verification-appliance.org][Verification appliance]], [[file:time-estimates.org][Time estimates]], [[file:sufficiency-flip.org][Sufficiency flip]], [[file:upgrade-lifecycle.org][Upgrade lifecycle]], [[file:lisp-economics.org][Lisp economics]]