Add two new nodes: Lisp Machine security (PMP/ECALL architecture) and Common Logic relevance analysis
This commit is contained in:
@@ -14,4 +14,4 @@ Every subdomain involved is software — the most codifiable domain. RISC-V ISA,
|
||||
|
||||
The Tenstorrent approach is dramatically simpler than FPGA because the microcode is RISC-V assembly (software), not FPGA bitstream (hardware with minutes-per-iteration synthesis).
|
||||
|
||||
See also: [[file:verification-appliance.org][Verification appliance]], [[file:time-estimates.org][Time estimates]], [[file:sufficiency-flip.org][Sufficiency flip]], [[file:upgrade-lifecycle.org][Upgrade lifecycle]], [[file:lisp-economics.org][Lisp economics]]
|
||||
See also: [[file:lisp-machine-security.org][Lisp Machine security]], [[file:verification-appliance.org][Verification appliance]], [[file:time-estimates.org][Time estimates]], [[file:sufficiency-flip.org][Sufficiency flip]], [[file:upgrade-lifecycle.org][Upgrade lifecycle]], [[file:lisp-economics.org][Lisp economics]]
|
||||
|
||||
Reference in New Issue
Block a user