chore: unify bold syntax to single asterisk in .org files and update legacy memex-amero references

projects/lisp_machine_bootstrap/docs/README.org

@@ -11,17 +11,17 @@ The Lisp Machine Bootstrap project aims to remove the "Unix/C Tax"—the layers
 
 * Philosophy: Tagged, Homoiconic, and Bare-Metal
 
-- **Hardware-Native Lisp:** Instruction Set Architecture (ISA) optimized for Lisp (CAR, CDR, CONS as hardware instructions).
-- **Tagged Memory:** Memory management handled by the hardware, preventing buffer overflows and memory corruption by design.
-- **Removing the C Core:** Eliminating the reliance on C-based kernels. The "Kernel" is a small Lisp bootstrapper.
-- **FPGA First:** Utilizing Field-Programmable Gate Arrays (FPGAs) as the initial prototyping environment.
+- *Hardware-Native Lisp:* Instruction Set Architecture (ISA) optimized for Lisp (CAR, CDR, CONS as hardware instructions).
+- *Tagged Memory:* Memory management handled by the hardware, preventing buffer overflows and memory corruption by design.
+- *Removing the C Core:* Eliminating the reliance on C-based kernels. The "Kernel" is a small Lisp bootstrapper.
+- *FPGA First:* Utilizing Field-Programmable Gate Arrays (FPGAs) as the initial prototyping environment.
 
 * The Bootstrap Path
 
-1. **Phase 1: Soft Machine (Current):** Emacs/CL running on Linux (The "Simulator").
-2. **Phase 2: Virtual Machine:** Develop a specialized Lisp VM that abstracts away the Linux kernel.
-3. **Phase 3: FPGA Implementation:** Port the VM to an FPGA core (Verilog/VHDL).
-4. **Phase 4: Sovereign Silicon:** Synthesize to a custom RISC-V or dedicated Lisp ASIC.
+1. *Phase 1: Soft Machine (Current):* Emacs/CL running on Linux (The "Simulator").
+2. *Phase 2: Virtual Machine:* Develop a specialized Lisp VM that abstracts away the Linux kernel.
+3. *Phase 3: FPGA Implementation:* Port the VM to an FPGA core (Verilog/VHDL).
+4. *Phase 4: Sovereign Silicon:* Synthesize to a custom RISC-V or dedicated Lisp ASIC.
 
 * Initial Research & Tasks