:PROPERTIES:
:ID:       3cf9b4e5-5956-4117-930d-cd4c86371373
:CREATED:  [2026-04-07 Tue 12:57]
:EDITED:   [2026-04-07 Tue 13:42]
:END:
#+TITLE: PROJECT: SDR Suite Lisp (Universal Literate Note)
#+STARTUP: content
#+FILETAGS: :radio:sdr:lisp:signal-processing:psf:

* Overview
The *SDR Suite Lisp* project aims to develop a comprehensive Software Defined Radio environment using Common Lisp. It leverages the high-performance, threaded nature of SBCL to provide real-time signal processing across various domains, from satellite communication to passive radar and computer networking.

* Phase A: Demand (PRD)
:PROPERTIES:
:STATUS: FROZEN
:END:

** 1. Purpose
Define the functional and technical requirements for a Lisp-native SDR architecture.

** 2. User Needs
- *Real-time Signal Processing:* High-performance DSP loops in Common Lisp.
- *Multimodal Support:* Unified framework for EME, ALE, SSTV, and standard Rx (FM/AM).
- *Extensibility:* Modular "plug-and-play" architecture for new decoders and protocols.
- *Hardware Agnostic:* Support for RTL-SDR, HackRF, and high-end FPGA-based SDRs.

** 3. Success Criteria
*** TODO Core DSP Loop Benchmarking (SBCL)
*** TODO RTL-SDR Driver Interface (via CFFI)
*** TODO Basic FM Broadcast Decoder Implementation
*** TODO Spectral Waterfall Visualization Stubs

* Phase B: Blueprint (PROTOCOL)
:PROPERTIES:
:STATUS: SIGNED
:END:

** 1. Architectural Intent
Interfaces for IQ stream processing and protocol dispatch. Source of truth is the physical signal and the DSP mathematical specifications.

** 2. Semantic Interfaces
#+begin_src lisp
(defun sdr-perceive-stream (source-id buffer-size)
  "Initializes the IQ sample stream from the hardware source.")

(defun sdr-decode-fm (iq-samples)
  "Applies de-emphasis and filtering to extract audio from IQ data.")
#+end_src

* Phase D: Build (Implementation)
Current implementation status is "Architecture Research." Placeholder for CFFI bindings and DSP libraries.

* Phase E: Chaos (Verification)
Verification involves signal fidelity audits and real-time latency testing under various CPU loads.