9b2be10c77
Replace monolithic passepartout-economics.org with directory of org-roam style nodes, each with :ID: property and cross-references using [[id:uuid][title]] format. 27 nodes organized by theme: - Core: index, triad overview, agora, stoa - Revenue: verification appliance, domain gate packages, evaluation harness, skill marketplace, agora usernames, PDS service, compute marketplace - Strategy: investment thesis, moats, licensing, patents, AI industry impact - Analysis: lisp economics, sufficiency flip, time estimates, cost structure, gate rule encoding, upgrade lifecycle, biology parallels, symbolics comparison - Big money: verification monopoly, infrastructure lock-in Old file kept as archive with redirect links to new structure.
18 lines
1.7 KiB
Org Mode
18 lines
1.7 KiB
Org Mode
:PROPERTIES:
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:ID: 13e6ae54-2d24-5aa0-b1cd-a7e8e749aa70
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:END:
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#+title: The Self-Driving Lisp Machine
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#+filetags: :passepartout:lisp-machine:hardware:riscv:tenstorrent:
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A Tenstorrent P150 (~72 RISC-V Tensix cores) running Passepartout: 72 RISC-V cores running Lisp microcode, one core dedicated to ACL2, one to Screamer, the rest to gate verification and fact store operations.
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The self-driving threshold: the system can synthesize and load its own FPGA microcode or Tensix dispatch programs from within the running Lisp image. The system profiles its own gate verification latency, proposes a new microcoded instruction for the hot path, compiles RISC-V assembly from ACL2-verified specifications, loads it via PCIe DMA from within SBCL, benchmarks it — and rolls back if slower.
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Every subdomain involved is software — the most codifiable domain. RISC-V ISA, SBCL internals, ACL2 metafunctions, CIC type theory, compiler optimization — all can flip to symbolic sufficiency within days to weeks of ingestion.
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**Timeline:** ~6,000 lines of new code (microcode, PCIe DMA, Tensix management, benchmark harness). ~60 cycles at current velocity. 2-4 weeks. Total from today: 6-10 weeks.
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The Tenstorrent approach is dramatically simpler than FPGA because the microcode is RISC-V assembly (software), not FPGA bitstream (hardware with minutes-per-iteration synthesis).
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See also: [[id:84a537b4-4256-50c8-91f5-dd5b4538418f][Verification appliance]], [[id:dc2e4f22-1c4c-5d4a-a151-f96e5d3b0d70][Time estimates]], [[id:efc76898-03f7-57ba-923d-35d65da88bb7][Sufficiency flip]], [[id:29e4dbf3-cf19-589c-8b14-389e8a39d564][Upgrade lifecycle]], [[id:9af13fff-9725-542b-93b1-a555bc74ad72][Lisp economics]]
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