cc3976fb7f
- Split competitive-analysis-2026-05.org → TOC + 9 competitor files in ideas/competitors/. Dropped date from filename. All competitor UUIDs generated, TOC keeps original UUID for backlink continuity. - Deleted passepartout-economics.org archive (replaced by 27-node KB). - Inlined 5 'See also' blocks into natural prose (compliance-index, first-mover-window, revenue-table, orders-of-magnitude-time, native-org-knowledge-base). - Linked 7 orphan compliance pages back to compliance index + finished truncated sentences. - Linked all 14 Agora requirement docs from topic-relevant pages (identity→lisp-machine-security, infrastructure→compute-marketplace, social-space→growth-strategy, exchange→agora-contracts, etc.). - Linked ai-industry-impact from investment-thesis, sufficiency-flip, verification-appliance, effects-growth-flywheel (up from 1 to 10+ pages). - Fixed CREATED timestamps to use git commit dates instead of today. - Made all links absolute from root (no port inheritance). - Removed stale agora/docs/ duplicate content.
18 lines
1.7 KiB
Org Mode
18 lines
1.7 KiB
Org Mode
:PROPERTIES:
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:CREATED: [2026-05-24 Sun]
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:ID: 84a537b4-4256-50c8-91f5-dd5b4538418f
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:END:
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#+title: Verification Appliance (Hardware)
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#+filetags: :passepartout:revenue:hardware:fpga:tenstorrent:
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An FPGA or Tenstorrent card pre-loaded with a mature [[id:28c46769-c14b-42aa-ac7a-69d310157f8f][Passepartout]] image, [[id:c34940cc-090e-57c4-8020-e78b1d32b96c][domain-specific gate rules]], and a hardware root of trust. No cloud dependency.
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**Target:** regulated industries needing [[id:45258a2d-1675-562c-9024-5d1eb2f1ea56][provable compliance]] that cannot accept cloud-based AI.
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**Price:** $5K-$50K/unit. **Volume:** hundreds to low thousands in year one.
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The [[id:13e6ae54-2d24-5aa0-b1cd-a7e8e749aa70][Lisp Machine]] on Tenstorrent P150 (~72 RISC-V Tensix cores on a PCIe card) is the realistic first target: the microcode is RISC-V assembly (software), not FPGA bitstream (hardware). The system can propose, load, test, and roll back a new dispatch routine in seconds. An FPGA path would add synthesis time (minutes to hours per iteration). This hardware-first approach embodies [[id:9af13fff-9725-542b-93b1-a555bc74ad72][Lisp economics]] — verification hardware has near-zero marginal cost. The [[id:29e4dbf3-cf19-589c-8b14-389e8a39d564][Upgrade lifecycle]] for the appliance is managed via signed firmware updates with Merkle snapshots.
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The [[id:6fe67db6-25bd-4d11-bd1d-b44ec809e858][Agora identity specification]] shows how the verification appliance issues provable identities for network participants. The [[id:5f55bbe6-d243-5766-8ccf-5c5cc88a6542][impact on the AI and GPU industry]] analysis covers how this new hardware tier — CPU-native Lisp microcode on RISC-V cores — reshapes the industry structure.
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Revenue estimate: 50 sales in year one = $250K-$2.5M.
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